1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor integrated circuit device, particularly, that in which a bipolar transistor and a CMOS transistor are formed on the same semiconductor substrate.
2. Description of the Related Art
Conventionally, where a Bi-CMOS semiconductor integrated circuit in which a bipolar transistor and a CMOS transistor are integrated on the same substrate is manufactured, as described in e.g. JP-A-3-262154, the steps of forming the bipolar transistor and CMOS transistor are commonized to reduce the number of fabricating steps.
Referring to step sectional views shown in FIGS. 28-48, an explanation will be given of the above conventional technique.
First, as shown in FIG. 28, using a resist pattern formed by photolithography (hereinafter, also referred to simply "resist pattern" or "resist") as a mask, ions of arsenic (As) or antimony (Sb) are implanted into a surface of a P-type silicon (Si) substrate 401. The resist pattern is removed by plasma ashing using oxygen gas (hereinafter referred to "oxygen plasma ashing") Thereafter, the substrate is heat-treated to form an N-type embedded collector layer 402a for a bipolar transistor and an N-type embedded well layer 402b for a P-channel MOS transistor.
As shown in FIG. 29, using a resist pattern as a mask, ions of boron (B) are implanted into the surface of the P-type Si substrate 401. This resist pattern is removed by oxygen plasma ashing. The Si substrate 401 is heat-treated to form P-type channel stopper layers 403a, 403b for the bipolar NPN transistor and P-type embedded well layer 403c for an N-channel MOS transistor.
As shown in FIG. 30, on the surface of the P-type Si substrate 401, an N-type epitaxial layer 404 doped with impurities of arsenic (As) or phosphorus (P) is grown at a temperature range of 1100-1200.degree. C.
As shown in FIG. 31, using a resist pattern as a mask, ions of phosphorus (P) are implanted into the surface of the N-type epitaxial layer 404. After the resist pattern is removed by oxygen plasma ashing, the Si substrate 401 is heat-treated at a temperature of about 1100.degree. C. to form a collector layer of the bipolar NPN transistor and an N-type well layer 405 serving as a well of the P-channel MOS transistor.
As shown in FIG. 32, using a resist pattern as a mask, ions of boron are implanted into the surface of the N-type epitaxial layer 404. After the resist pattern is removed, the Si substrate 401 is heat-treated to form-a P-type well layer 406 serving as a well of the N-channel MOS transistor.
As shown in FIG. 33, on the surface of the N-type epitaxial layer 404 in which P-type well layer 406 and N-type well layer 405 are formed (hereinafter, also referred to simply "N-type epitaxial layer 404" ), a silicon oxide film 407 is formed by thermal oxidation and a silicon nitride film 408 is formed by reduced-pressure CVD.
As shown in FIG. 34, using a resist pattern as a mask on the silicon nitride film 408, the silicon nitride film 408, oxide film 407 and N-type epitaxial layer 404 are successively etched to form silicon trenches 409a-409e. And then the resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 35, by thermal oxidation, oxide film 410 is formed on the bottom and side wall of each of the silicon trenches 409a-409e.
As shown in FIG. 36, the above silicon nitride film is anisotropically etched to form a side wall silicon nitride film 412 on the respective side walls of the silicon trenches 409a-409e.
As shown in FIG. 37, using the silicon nitride film 408 and the silicon nitride film 412 formed on the side wall of the trenches 409a-409e as a mask, the silicon trenches 409a-409e are thermally oxidized in a temperature range of 1000-1100.degree. C. to form element isolation LOCOS films 413a-413e which reach the P-type silicon substrate 401. Thereby the N-type well layer 405 is separated to plurality of N-type well layer 405a-405e.
The silicon nitride film 408 and 412 are removed using phosphoric acid solution, and thereafter the oxide films 407a-407d are removed using a mixed solution of ammonium fluoride (NH.sub.4 F) and hydrofluoric acid (HF).
As shown in FIG. 38,using a resist pattern formed on the N-type epitaxial layer 404 as a mask, ions of phosphorus (P) are implanted to form an anti-punch-through layer 414 for the P-channel MOS transistor in the N-type well layer 405c of the P-channel MOS transistor. Ions of boron (B) are ion-implanted to introduce impurities 416 for controlling the threshold voltage of the P channel MOS transistor. Thereafter, the resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 39,using a resist pattern formed on the N-type epitaxial layer 404 as a mask, ions of boron (B) are implanted to form an anti-punch-through layer 415 for the N-channel MOS transistor in the P-type well layer 406 of the P-channel MOS transistor. Ions of boron (B) are ion-implanted to introduce impurities 417 for controlling the threshold voltage of the N-channel MOS transistor. Thereafter, the resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 40,using a resist pattern as a mask, ions of boron (B) are selectively implanted into the surface of the N-type epitaxial layer 404. After the resist pattern is removed, the Si-substrate is heat-treated to form a base layer 418 of the NPN bipolar transistor in the N-type well layer 405b as a collector layer of the NPN bipolar transistor.
As shown in FIG. 41, by thermal oxidation, gate oxide film 419 is formed on the N-type epitaxial layer 404. Thereafter, on the N-type epitaxial layer 404, using a resist pattern as a mask and a mixed solution of ammonium fluoride (NH.sub.4 F) and hydrofluoric acid (HF), the gate oxide film on emitter region of the NPN bipolar transistor is selectively removed to form an emitter electrode extracting opening 420. The resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 42, on the entire surface of the N-type epitaxial layer 404, apolycrystalline silicon (Si) film is formed by reduced pressure CVD, and arsenic (As) or phosphorus (P) is ion-implanted to introduce impurities in the polycrystalline silicon film. After a CVD film is grown on the entire surface, using a resist pattern as a mask, the CVD oxide film and polycrystalline silicon (Si) film are etched by anisotropic dry etching to form a emitter electrode 421, an oxide film thereon 423, a gate electrode 422a, 422b and an oxide film 423b, 423c thereon. The resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 43, using as a mask a resist pattern and gate electrode 422a of the P-channel MOS transistor and oxide film 423b thereon, boron (B) is ion-implanted to a LLD layer 424 of the P-channel MOS transistor. Therefore, the resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 44, using as a mask a resist pattern and gate electrode 422b of the N-channel MOS transistor and oxide film 423c thereon, phosphorus (P) is ion-implanted to form a LLD layer 425 of the N-channel MOS transistor. Therefore, the resist attern is removed by oxygen plasma ashing.
Finally, as shown in FIG. 45, the CVD oxide film formed on the entire surface are anisotropically etched to form side wall oxide films 426 on the side walls of the emitter electrode 421 and gate electrodes 422a and 422b.
As shown in FIG. 46, using as a mask a resist pattern, the oxide film 423a on the emitter electrode 421 and the oxide film 423b on the gate electrodes and side wall oxide film 426 on the side walls, boron is ion-implanted to form an external base layer 427 of the NPN transistor and a source/drain layer 428 of the P-channel MOS transistor. The resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 47, using as a mask a resist pattern, the oxide film 423c on the gate electrode 422b and side wall oxide film 426 on the corresponding side wall, boron is ion-implanted to form a corrector contact layer 430 of the NPN transistor and a source/drain layer 429 of the N-channel MOS transistor. The resist pattern is removed by oxygen plasma ashing.
As shown in FIG. 48, heat treatment is carried out in an atmosphere of nitrogen at a temperature so that arsenic (As) in the emitter electrode 421 of the NPN bipolar transistor is diffused into the base layer 418 through the opening 420 for extending the emitter electrode thereby to form the emitter layer 431.
As described above, Bi-CMOS semiconductor integrated circuit is fabricated, and in the above described technique, the step of forming the N-type embedded collector 402a of the bipolar transistor and N-type embedded well layer 402b of the P-channel MOS transistor; the step of forming the P-type embedded channel stopper layer 403a, 403b of the bipolar transistor and P-type embedded well layer 403c of the N-channel MOS transistor; the step of forming the collector layer of the bipolar transistor and well layer of the P-channel MOS transistor; the step of forming the emitter electrode 421 and gate electrode 422a, 422b; the step of forming the external base layer 427 of the bipolar transistor and source/drain layer 428 of the P-channel MOS transistor, are performed by a same step respectively. In this way, the number of fabricating steps could be reduced.
When miniaturization of a Bi-CMOS integrated circuit is intended for high integration, high speed and low power consumption, miniaturization of an element isolation region is important. In the conventional method of fabricating a semiconductor device, by impurity diffusing transversally in the following heat treatment step, embedded channel stopper layer below a element isolation film forms a junction with the embedded collector layer with a high impurity concentration so that the junction capacitance between the collector and substrate of the NPN transistor is increased. That is to say, the P-type embedded channel stopper layers 403a, 403b immediately below the element isolation LOCOS films 413a and 413c reaching the P-type Si substrate 401 of the bipolar transistor are diffused transversely in parallel to the surface of the Si substrate 401 by heat treatment at a high temperature over about 1100.degree. C., for e.g. growing the epitaxial layer 404 after the embedded channel stopper has been formed, for forming the N-type well 405 and P-type well 406 and for forming the element isolation LOCOS films 413a-413e. This forms a junction with the N-type embedded collector layer 402a with a high impurity concentration so that the junction capacitance between the collector and substrate of the NPN transistor is increased and the high frequency characteristic of the NPN transistor is lowered. Further, the presence of the anti-punch-through layer 415 of the N-channel MOS transistor by ion implantation by boron increases the number of steps leading to cost enhancement.